decoder_74ls138.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 34 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY decoder_74LS138 IS 
           PORT (g1,g2a,g2b  : IN  std_logic;
                 a,b,c: IN  std_logic;
		 y    : OUT std_logic_vector(7 DOWNTO 0));
END decoder_74LS138;

ARCHITECTURE rtl_arc OF decoder_74LS138 IS
     SIGNAL  comb  : std_logic_vector(2 DOWNTO 0);
BEGIN
     comb <= c & b & a;
     PROCESS (g1,g2a,g2b,comb)
     BEGIN
          IF (g1 = '1' AND g2a = '0' AND g2b = '0') THEN
              CASE comb IS
                   WHEN "000" => y <= "11111110";
                   WHEN "001" => y <= "11111101";
                   WHEN "010" => y <= "11111011";
                   WHEN "011" => y <= "11110111";
                   WHEN "100" => y <= "11101111";
                   WHEN "101" => y <= "11011111";
                   WHEN "110" => y <= "10111111";
                   WHEN "111" => y <= "01111111";
                   WHEN OTHERS => y  <= "XXXXXXXX";
              END CASE;
          ELSE
              y <= "11111111";
          END IF;
     END PROCESS;
END rtl_arc;