and3_gate.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY and3_gate IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
                 c  : IN  std_logic;
		 y  : OUT std_logic);
END and3_gate;

ARCHITECTURE behave_arc OF and3_gate IS
BEGIN
     PROCESS(a,b,c)
     BEGIN
	  y <= a AND b AND c;
     END PROCESS;
END behave_arc;