bidir_bus_buff8.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY bidir_bus_buff8 IS 
           PORT (a,b  : INOUT std_logic_vector(7 DOWNTO 0);
                 en   : IN    std_logic;
                 dr   : IN    std_logic);
END bidir_bus_buff8;

ARCHITECTURE rtl_arc OF bidir_bus_buff8 IS
     signal aout,bout : std_logic_vector(7 DOWNTO 0);
BEGIN
     PROCESS (a,b,dr,en)
     BEGIN
          IF (en = '0' AND dr = '1') THEN
              bout <= a;
          ELSIF (en = '0' AND dr = '0') THEN
              aout <= b;
          ELSE
              aout <= "ZZZZZZZZ";
              bout <= "ZZZZZZZZ";
          END IF;
          b <= bout;
          a <= aout;
     END PROCESS;
END rtl_arc;