equal_comp4.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY equal_comp4 IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
		 q  : OUT std_logic);
END equal_comp4;

ARCHITECTURE behave_arc OF equal_comp4 IS
BEGIN
     PROCESS (a,b)
     BEGIN
          IF (a = b) THEN
              q <= '1';
          ELSE
              q <= '0';
          END IF;
     END PROCESS;
END behave_arc;