and2_gate.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY and2_gate IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
	         c  : OUT std_logic);
END and2_gate;

ARCHITECTURE behave_arc OF and2_gate IS
BEGIN
     PROCESS(a,b)
     BEGIN
	  c <= a AND b;
     END PROCESS;
END behave_arc;