pri_encoder.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 59 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY pri_encoder IS 
           PORT (d  : IN  std_logic_vector(7 DOWNTO 0);
                 e1 : IN  std_logic;
                 q  : OUT std_logic_vector(2 DOWNTO 0);
		 gs,e0  : OUT std_logic);
END pri_encoder;

ARCHITECTURE rtl_arc OF pri_encoder IS
BEGIN
     PROCESS (e1,d)
     BEGIN
          IF (e1 = '1') THEN
              q <= "111";
              gs <= '1';
              e0 <= '1';
          ELSIF ( d = "11111111"  AND  e1 = '0') 	THEN
              q <= "111";
              gs <= '1';
              e0 <= '0';
          ELSIF ( d(7) = '0'  AND   e1 = '0') 	THEN
              q <= "000";
              gs <= '0';
              e0 <= '1';
          ELSIF ( d(6) = '0'  AND   e1 = '0')   THEN
              q <= "001";
              gs <= '0';
              e0 <= '1';
          ELSIF ( d(5) = '0'  AND   e1 = '0') 	THEN
              q <= "010";
              gs <= '0';
              e0 <= '1';
          ELSIF ( d(4) = '0'  AND   e1 = '0') 	THEN
              q <= "011";
              gs <= '0';
              e0 <= '1';
          ELSIF ( d(3) = '0'  AND   e1 = '0') 	THEN
              q <= "100";
              gs <= '0';
              e0 <= '1';
          ELSIF ( d(2) = '0'  AND   e1 = '0') 	THEN
              q <= "101";
              gs <= '0';
              e0 <= '1';
          ELSIF ( d(1) = '0'  AND   e1 = '0') 	THEN
              q <= "110";
              gs <= '0';
              e0 <= '1';
          ELSIF ( d(1) = '0'  AND   e1 = '0') 	THEN
              q <= "111";
              gs <= '0';
              e0 <= '1';
          END IF;
     END PROCESS;
END rtl_arc;