comparison.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY comparison IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
		 q  : OUT std_logic_vector(2 DOWNTO 0));
END comparison;

ARCHITECTURE behave_arc OF comparison IS
BEGIN
     PROCESS (a,b)
     BEGIN
          IF (a = b) THEN
              q <= "001";
          ELSIF (a > b) THEN
              q <= "010";
          ELSE
              q <= "100";
          END IF;
     END PROCESS;
END behave_arc;