and2_gate.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY and2_gate IS 
           PORT (a  : IN  std_logic;
                 b  : IN  std_logic;
	         c  : OUT std_logic);
END and2_gate;

ARCHITECTURE rtl_arc OF and2_gate IS
BEGIN
     PROCESS (a,b)
     VARIABLE  comb  : std_logic_vector(1 DOWNTO 0);
     BEGIN
          comb := a & b;
          CASE comb IS
               WHEN "00" => c <= '0';
               WHEN "01" => c <= '0';
               WHEN "10" => c <= '0';
               WHEN "11" => c <= '1';
               WHEN OTHERS => c <= 'X';
          END CASE;
     END PROCESS;
END rtl_arc;