tri_gate.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY tri_gate IS 
           PORT (din  : IN  std_logic;
                 en   : IN  std_logic;
		 dout : OUT std_logic);
END tri_gate;

ARCHITECTURE behave_arc OF tri_gate IS
BEGIN
     PROCESS (din,en)
     BEGIN
          IF (en = '1') THEN
              dout <= din;
          ELSE
              dout <= 'Z';
          END IF;
     END PROCESS;
END behave_arc;