kcoun101.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 48 行

LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;

ENTITY kcoun101 IS
           PORT (A  : IN  std_logic;
                 B  : OUT  std_logic);
END kcoun101;

ARCHITECTURE kcoun101_arc OF kcoun101 IS
     COMPONENT kcoun10
          PORT (A  : IN  std_logic;
                B  : OUT std_logic);
     END COMPONENT;
     SIGNAL  tmp1,tmp2  : std_logic;
BEGIN
     U0: kcoun10   PORT MAP(A,tmp1);
     U1: kcoun10   PORT MAP(tmp1,tmp2);
     U2: kcoun10   PORT MAP(tmp2,B);
END kcoun101_arc;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY kcoun10 IS
           PORT (A  : IN  std_logic;
                 B  : OUT  std_logic);
END kcoun10;

ARCHITECTURE kcoun10_arc OF kcoun10 IS
     SIGNAL  counter  : std_logic;
BEGIN
     PROCESS(A)
     VARIABLE  counter1  : integer RANGE 0 TO 15;
     CONSTANT  md  : integer := 5;
     BEGIN
          IF (A'event AND A = '1') THEN
             IF (counter1 = md) THEN
                 counter1 := 0;
                 counter <= NOT counter;
                 B <= counter;
             END IF;
             counter1 := counter1+1;
          END IF; 
     END PROCESS;
END kcoun10_arc;