control.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 98 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE state_pack IS
        TYPE state IS (QA,QB,QC,QD,QE,QF);
END state_pack;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.state_pack.ALL;

ENTITY control IS
           PORT (A,B,C,D,E,F,G,CLK  : IN  std_logic;
                 H,I,J,K,L,M        : OUT  std_logic);
END control;

ARCHITECTURE control_arc OF control IS
     SIGNAL  current_state  : state := QA;
BEGIN
     PROCESS
     BEGIN
          WAIT UNTIL CLK'event AND CLK ='1';
          M <= '1';
          CASE current_state  IS
                WHEN QA => H <= '0';
                     IF (A ='0') THEN
                         current_state <= QA;
                     ELSE
                         current_state <= QB;
                         M <= '0'; L <= '1'; K <= '1';
                     END IF;

                WHEN QB => M <= '1'; H <= '0';
                     IF (C ='0') THEN
                         current_state <= QB;
                     ELSE
                         current_state <= QC;
                         J <= '1';
                     END IF;

                WHEN QC => J <= '0'; I <= '0'; H <= '1';
                     IF (D ='1') THEN
                         current_state <= QF;
                         K <= '0';
                     ELSIF (C ='1') THEN
                         current_state <= QC;
                         J <= '1';
                     ELSIF (G ='1') THEN
                         current_state <= QD;
                     ELSIF (E ='0') THEN
                         current_state <= QC;
                     ELSE 
                         I <= '1';
                         IF (F ='0') THEN
                             current_state <= QE;
                         ELSIF (G ='1') THEN
                             current_state <= QD;
                         ELSE
                             current_state <= QC;
                         END IF;
                     END IF;

                WHEN QD => H <= '1';
                     IF (E ='1') THEN
                         current_state <= QE;
                     ELSIF (C ='1') THEN
                         current_state <= QC;
                         J <= '1';
                     ELSIF (D ='0') THEN
                         current_state <= QD;
                     ELSE
                         L <= '0';
                         current_state <= QA;
                     END IF;

                WHEN QE => H <= '1';
                     IF (C ='1') THEN
                         current_state <= QC;
                         J <= '1';
                     ELSIF (D ='0') THEN
                         current_state <= QE;
                     ELSE
                         K <= '0';
                         current_state <= QF;
                     END IF;

                WHEN QF => H <= '0';
                     IF (B ='0') THEN
                         current_state <= QF;
                     ELSE
                         current_state <= QB;
                         K <= '1'; M <= '0';
                     END IF;
          END CASE; 
     END PROCESS;
END control_arc;