full_adder.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 20 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY full_adder IS 
        PORT (A,B : IN  std_logic;
              Cin : IN  std_logic;
              Co  : OUT std_logic;
              S   : OUT std_logic);
END full_adder; 

ARCHITECTURE rtl OF full_adder IS
         SIGNAL  tmp1,tmp2  : std_logic; 
BEGIN
	     tmp1 <= A XOR B;
	     tmp2 <= tmp1 AND Cin;
	     S <= tmp1 XOR Cin;
	     Co <= tmp2 OR (A AND B);
END rtl;