and_gate4.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY and_gate4 IS 
           PORT (a,b,c,d  : IN  std_logic;
                       q  : OUT std_logic);
END and_gate4;

ARCHITECTURE behave OF and_gate4 IS
         COMPONENT and_gate
            GENERIC (delay  : time);
            PORT (a  : IN  std_logic;
                  b  : IN  std_logic;
		  c  : OUT std_logic);
         END COMPONENT;
         SIGNAL  q1,q2  : std_logic;
BEGIN
	U1:and_gate GENERIC MAP (5 ns)
             PORT MAP (a,b,q1);
	U2:and_gate GENERIC MAP (6 ns)
             PORT MAP (c,d,q2); 
	U3:and_gate GENERIC MAP (7 ns)
             PORT MAP (q1,q2,q); 
END behave;