half_adder.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY half_adder IS 
       PORT ( A,B : IN  std_logic;
              Co  : OUT std_logic;
              S   : OUT std_logic);
END half_adder; 

ARCHITECTURE rtl OF half_adder IS
      SIGNAL tmp1,tmp2 : std_logic;
BEGIN
	     tmp1 <= A OR B;
	     tmp2 <= A NAND B;
	     Co  <= NOT tmp1;
	     S   <= tmp1 AND tmp2;
END rtl;