dff.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY dff IS 
           PORT (d   : IN  std_logic;
                 clk : IN  std_logic;
		 q   : OUT std_logic);
END dff;

ARCHITECTURE rtl OF dff IS
BEGIN
     PROCESS (clk)
     BEGIN
          IF ((NOT(clk'stable)) AND clk = '1') THEN
              q <= d;
          END IF;
     END PROCESS;
END rtl;