vector_to_int.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 19 行

FUNCTION vector_to_int
            (input  : IN  std_logic_vector) RETURN integer IS
         VARIABLE  result,temp  : integer := 0;
BEGIN
         FOR i IN 0 TO input'length-1 LOOP
             temp := 0;
             IF (input(i)= '1') THEN
                 temp := 2**i;
             ELSE
                 ASSERT (input(i)= '0')
                 REPORT "can not convert std_logic_vector to integer."
                 SEVERITY warning;
             END IF;
             result := result + temp;
         END LOOP;
         RETURN (result);
END vector_to_int;