dff.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY dff IS 
           PORT (d   : IN  std_logic;
                 clk : IN  std_logic;
		 q   : OUT std_logic);
END dff;

ARCHITECTURE rtl OF dff IS
BEGIN
     bad:
     BLOCK(clk'event AND clk = '1')
     BEGIN
          q <= GUARDED d;
     END BLOCK bad;
END rtl;