max.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE example IS
        FUNCTION maximum (a,b  : std_logic) RETURN std_logic;
        FUNCTION maximum (a,b  : bit) RETURN bit;
        FUNCTION maximum (a,b  : integer) RETURN integer;
END example;

PACKAGE BODY example IS
           FUNCTION maximum 
                    (a,b  : std_logic) RETURN std_logic IS
                VARIABLE  temp  : std_logic;
           BEGIN
                IF (a > b) THEN
                   temp := a;
                ELSE
                   temp := b;
                END IF;
                RETURN (temp);
           END maximum;

           FUNCTION maximum 
                    (a,b  : bit) RETURN bit IS
                VARIABLE  temp  : bit;
           BEGIN
                IF (a > b) THEN
                   temp := a;
                ELSE
                   temp := b;
                END IF;
                RETURN (temp);
           END maximum;

           FUNCTION maximum 
                    (a,b  : integer) RETURN integer IS
                VARIABLE  temp  : integer;
           BEGIN
                IF (a > b) THEN
                   temp := a;
                ELSE
                   temp := b;
                END IF;
                RETURN (temp);
           END maximum;
END example;


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.example.ALL;

ENTITY max IS 
           PORT (a1,b1 : IN  std_logic;
                 a2,b2 : IN  bit;
                 a3,b3 : IN  integer;
                 c1    : OUT std_logic;
                 c2    : OUT bit;
				 c3    : OUT integer);
END max;

ARCHITECTURE max_arc OF max IS
BEGIN
         c1 <= maximum (a1,b1);
         c2 <= maximum (a2,b2);
         c3 <= maximum (a3,b3);
END max_arc;