dff.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY dff IS 
           PORT (d,clk  : IN  std_logic;
		 q,qb   : OUT std_logic);
END dff;

ARCHITECTURE rtl OF dff IS
BEGIN
         block1: BLOCK(clk ='1')
         BEGIN
              q <= GUARDED d AFTER 3 ns;
              qb <= GUARDED (NOT d) AFTER 5 ns;
         END BLOCK block1;
END rtl;