convert.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 38 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY convert IS 
           PORT (i1  : IN  std_logic_vector(7 DOWNTO 0);
                 i2  : IN  std_logic_vector(7 DOWNTO 0);
                 f1  : OUT boolean;
                 f2  : OUT boolean;
                 o1  : INOUT integer;
				 o2  : INOUT integer);
END convert;

ARCHITECTURE behave OF convert IS
    PROCEDURE vector_to_int
                 (input  : IN  std_logic_vector;
                  SIGNAL flag : OUT boolean;
                  SIGNAL q    : INOUT integer) IS
    BEGIN
              q <= 0;
              flag <= false;
              FOR i IN input'RANGE LOOP
                  q <= q * 2;
                  IF (input(i)= '1') THEN
                     q <= q+1;
                  ELSIF (input(i)/= '0') THEN
                     flag <= true;
                  END IF;
              END LOOP;
    END vector_to_int;
BEGIN
         vector_to_int(i1,f1,o1);
         PROCESS (i2)
         BEGIN
              vector_to_int(i2,a,b);             
         END PROCESS;
END behave;