example.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE example IS
    PROCEDURE vector_to_int
              (input  : IN    std_logic_vector;
               flag   : OUT   boolean;
               q      : INOUT integer);
END PACKAGE example;

PACKAGE BODY example IS
    PROCEDURE vector_to_int
              (input  : IN    std_logic_vector;
               flag   : OUT   boolean;
               q      : INOUT integer) IS
    BEGIN
             q := 0;
             flag := false;
             FOR i IN input'RANGE LOOP
                 q := q * 2;
                 IF (input(i)= '1') THEN
                    q := q+1;
                 ELSIF (input(i)/= '0') THEN
                    flag := true;
                 END IF;
             END LOOP;
    END vector_to_int;
END PACKAGE BODY example;