example.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 42 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

PACKAGE example IS
        FUNCTION "+" (l,r  : integer) RETURN integer;
        FUNCTION "+" (l,r  : bit_vector) RETURN integer;
        FUNCTION "+" (l,r  : std_logic_vector) RETURN integer;
END example;

PACKAGE BODY example IS
            FUNCTION vector_to_int
                     (input  : IN  bit_vector) RETURN integer IS
                 VARIABLE  result,temp  : integer := 0;
            BEGIN
                 FOR i IN input'low TO input'high LOOP
                     temp := 0;
                     IF (input(i)= '1') THEN
                        temp := 2**(i- input'low);
                     END IF;
                     result := result + temp;
                 END LOOP;
                 RETURN (result);
            END vector_to_int;

            FUNCTION "+" (l,r  : integer) RETURN integer IS
            BEGIN
                 RETURN (l+r);
            END;

            FUNCTION "+" (l,r  : bit_vector) RETURN integer IS
            BEGIN
                 RETURN (vector_to_int(l)+ vector_to_int(r));
            END;

            FUNCTION "+" (l,r  : std_logic_vector) RETURN integer IS
            BEGIN
                 RETURN (conv_integer(l)+conv_integer(r));
            END;
END example;