example.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 60 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE example IS
        FUNCTION maximum (a,b  : integer) RETURN integer;
        FUNCTION maximum (a,b,c  : integer) RETURN integer;
        FUNCTION maximum (a,b,c,d  : integer) RETURN integer;
END example;

PACKAGE BODY example IS
           FUNCTION maximum (a,b  : integer) RETURN integer IS
                VARIABLE  temp  : integer;
           BEGIN
                IF (a > b) THEN
                   temp := a;
                ELSE
                   temp := b;
                END IF;
                RETURN (temp);
           END maximum;

           FUNCTION maximum (a,b,c: integer) RETURN integer IS
                VARIABLE  temp1, temp2  : integer;
           BEGIN
                IF (a > b) THEN
                   temp1 := a;
                ELSE
                   temp1 := b;
                END IF;
                IF (temp1 > c) THEN
                   temp2 := temp1;
                ELSE
                   temp2 := c;
                END IF;
                RETURN (temp2);
           END maximum;

           FUNCTION maximum (a,b,c,d: integer) RETURN integer IS
                VARIABLE  temp1,temp2,temp3 : integer;
           BEGIN
                IF (a > b) THEN
                   temp1 := a;
                ELSE
                   temp1 := b;
                END IF;
                IF (temp1 > c) THEN
                   temp2 := temp1;
                ELSE
                   temp2 := c;
                END IF;
                IF (temp2 > d) THEN
                   temp3 := temp2;
                ELSE
                   temp3 := d;
                END IF;
                RETURN (temp3);
           END maximum;
END example;