example.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 48 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE example IS
        FUNCTION maximum (a,b  : std_logic) RETURN std_logic;
        FUNCTION maximum (a,b  : bit) RETURN bit;
        FUNCTION maximum (a,b  : integer) RETURN integer;
END example;

PACKAGE BODY example IS
           FUNCTION maximum 
                    (a,b  : std_logic) RETURN std_logic IS
                VARIABLE  temp  : std_logic;
           BEGIN
                IF (a > b) THEN
                   temp := a;
                ELSE
                   temp := b;
                END IF;
                RETURN (temp);
           END maximum;

           FUNCTION maximum 
                    (a,b  : bit) RETURN bit IS
                VARIABLE  temp  : bit;
           BEGIN
                IF (a > b) THEN
                   temp := a;
                ELSE
                   temp := b;
                END IF;
                RETURN (temp);
           END maximum;

           FUNCTION maximum 
                    (a,b  : integer) RETURN integer IS
                VARIABLE  temp  : integer;
           BEGIN
                IF (a > b) THEN
                   temp := a;
                ELSE
                   temp := b;
                END IF;
                RETURN (temp);
           END maximum;
END example;