sync_communication.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY sync_communication IS 
           PORT (clk  : IN  std_logic;
		 irq  : OUT std_logic);
END sync_communication;

ARCHITECTURE rtl OF sync_communication IS
         SIGNAL  counter  : std_logic_vector(3 DOWNTO 0);
BEGIN
	 label1:PROCESS(clk)
         BEGIN
              IF (clk'event AND clk='1') THEN
                  counter <= counter+1;
              END IF;
         END PROCESS label1;

         label2:PROCESS(clk)
         BEGIN
              IF (clk'EVENT AND clk='1') THEN
                  IF (counter ="1111") THEN
                      irq <= '0';
                  ELSE
                      irq <= '1';
                  END IF;
              END IF;
         END PROCESS label2;
    END rtl;