vector_to_int.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 18 行

PROCEDURE vector_to_int
             (input  : IN    std_logic_vector;
              flag   : OUT   boolean;
              q      : INOUT integer) IS
BEGIN
         q := 0;
         flag := false;
         FOR i IN input'RANGE LOOP
             q := q * 2;
             IF (input(i)= '1') THEN
                q := q+1;
             ELSIF (input(i)/= '0') THEN
                flag := true;
             END IF;
         END LOOP;
END vector_to_int;