example.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

PACKAGE example IS
    FUNCTION vector_to_int
             (input  : IN  std_logic_vector) RETURN integer;
END PACKAGE example;

PACKAGE BODY example IS
    FUNCTION vector_to_int
             (input  : IN  std_logic_vector) RETURN integer IS
             VARIABLE  result,temp  : integer := 0;
    BEGIN
             FOR i IN input'low TO input'high LOOP
                 temp := 0;
                 IF (input(i)= '1') THEN
                     temp := 2**(i- input'low);
                 ELSE
                     ASSERT (input(i)= '0')
                     REPORT "can not convert std_logic_vector to integer."
                     SEVERITY warning;
                 END IF;
                 result := result + temp;
             END LOOP;
             RETURN (result);
    END vector_to_int;
END PACKAGE BODY example;