dff.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 20 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY dff IS 
           PORT (d,clk  : IN  std_logic;
	         q,qb   : OUT std_logic);
END dff;

ARCHITECTURE rtl OF dff IS
BEGIN
	 P1:PROCESS (clk)
         BEGIN
              IF (clk'event AND clk ='1') THEN
                  q  <= d;
                  qb <= NOT d;
              END IF;
         END PROCESS P1;
END rtl;