store_controller.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 60 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY store_controller IS 
           PORT (ready : IN  std_logic;
                 reset : IN  std_logic;
                 clk   : IN  std_logic;
                 read_write  : IN  std_logic;
		 we,oe       : OUT std_logic);
END store_controller;

ARCHITECTURE state_machine OF store_controller IS
     TYPE state_type IS (idle,decision,read,write);
     SIGNAL present_state,next_state  : state_type;
BEGIN
     state_transfer:PROCESS (reset,present_state,ready,read_write)
     BEGIN
        IF (reset ='1') THEN 
            oe <= '-';
            we <= '-';
            next_state <= idle;
        ELSE
          CASE present_state IS
               WHEN idle => we <='0';	oe <= '0';
                            IF (ready ='1') THEN
                                next_state <= decision;
                            ELSE
                                next_state <= idle;
                            END IF;
               WHEN decision => we <= '0';	oe <= '0';
                                IF (read_write ='1') THEN
                                    next_state <= read;
                                ELSE
                                    next_state <= write;
                                END IF;
               WHEN read => we <= '0';	oe <= '1';
                            IF (ready ='1') THEN
                                next_state <= idle;
                            ELSE
                                next_state <= read;
                            END IF;
               WHEN write => we <= '1';	oe <= '0';
                             IF (ready ='1') THEN
                                next_state <= idle;
                             ELSE
                                next_state <= write;
                             END IF;
          END CASE;
        END IF;
     END PROCESS;

     state_register:PROCESS (clk)
     BEGIN
          IF (clk'event AND clk ='1') THEN
              present_state <= next_state;
          END IF;
     END PROCESS;
END state_machine;