registern.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY registerN IS
           GENERIC (n : integer :=8);
           PORT (d   : IN  std_logic_vector(n-1 DOWNTO 0);
                 en  : IN  std_logic;
                 clk : IN  std_logic;
                 set,reset : IN  std_logic;
		 q   : BUFFER std_logic_vector(n-1 DOWNTO 0));
END registerN;

ARCHITECTURE rtl_arc OF registerN IS
BEGIN
	 PROCESS (clk)
         BEGIN
              IF (set ='0' AND reset ='1') THEN
                 q <= (OTHERS => '1');
              ELSIF (set ='1' AND reset ='0') THEN
                 q <= (OTHERS => '0');
              ELSIF (clk'event AND clk ='1') THEN
                 IF (en ='1') THEN 
                     q <= d;
                 ELSE
                     q <= q;
                 END IF;
              END IF;
         END PROCESS;
END rtl_arc;