latch_74ls373.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY latch_74LS373 IS 
           PORT (d    : IN  std_logic_vector(7 DOWNTO 0);
                 oe,g : IN  std_logic;
		 q    : INOUT std_logic_vector(7 DOWNTO 0));
END latch_74LS373;

ARCHITECTURE rtl_arc OF latch_74LS373 IS
BEGIN
	 PROCESS (oe,g)
         BEGIN
              IF (oe ='0') THEN
                  IF (g ='1') THEN 
                      q <= d;
                  ELSE
                      q <= q;
                  END IF;
              ELSE
                  q <= "ZZZZZZZZ";
              END IF;
         END PROCESS;
END rtl_arc;