async_rsjkff.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY async_rsjkff IS 
           PORT (j,k   : IN  std_logic;
                 clk   : IN  std_logic;
                 set   : IN  std_logic;
                 reset : IN  std_logic;
		 q,qb  : OUT std_logic);
END async_rsjkff;

ARCHITECTURE rtl_arc OF async_rsjkff IS
     SIGNAL q_temp,qb_temp : std_logic;
BEGIN
	 PROCESS (clk,set,reset)
         BEGIN
              IF (set ='0' AND reset ='1') THEN
                  q_temp  <= '1';
                  qb_temp <= '0';
              ELSIF (set ='1' AND reset ='0') THEN
                  q_temp  <= '0';
                  qb_temp <= '1';
              ELSIF (clk'event AND clk ='1') THEN
                  IF (j ='0' AND k ='1') THEN 
                      q_temp  <= '0';
                      qb_temp <= '1';
                  ELSIF (j ='1' AND k ='0') THEN
                      q_temp  <= '1';
                      qb_temp <= '0';
                  ELSIF (j ='1' AND k ='1') THEN
                      q_temp  <= NOT q_temp;
                      qb_temp <= NOT qb_temp;
                  END IF;
              END IF;
              q  <= q_temp;
              qb <= qb_temp;
         END PROCESS;
END rtl_arc;