counter.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY counter IS 
           PORT (clk    : IN  std_logic;
                 areset : IN  std_logic;
                 sset   : IN  std_logic;
                 enable : IN  std_logic;
                 cout   : OUT  std_logic;
		 q      : BUFFER std_logic_vector(3 DOWNTO 0));
END counter;

ARCHITECTURE rtl_arc OF counter IS
BEGIN
     PROCESS (clk,areset)
     BEGIN
          IF (areset ='1') THEN
              q <= (OTHERS => '0');
          ELSIF (clk'event AND clk ='1') THEN
              IF (sset ='1') THEN
                  q <= "1010";
              ELSIF (enable ='1') THEN
                  q <= q +1;
              ELSE
                  q <= q;
              END IF;
          END IF;
     END PROCESS;
     cout <= '1' WHEN q = "1111" AND enable ='1'
              ELSE '0';
END rtl_arc;