async_rsdff.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY async_rsdff IS 
           PORT (d,clk : IN  std_logic;
                 set   : IN  std_logic;
                 reset : IN  std_logic;
		 q,qb  : OUT std_logic);
END async_rsdff;

ARCHITECTURE rtl_arc OF async_rsdff IS
BEGIN
	 PROCESS (clk,set,reset)
         BEGIN
              IF (set ='0' AND reset ='1') THEN
                  q  <= '1';
                  qb <= '0';
              ELSIF (set ='1' AND reset ='0') THEN
                  q  <= '0';
                  qb <= '1';
              ELSIF (clk'event AND clk ='1') THEN
                  q  <= d;
                  qb <= NOT d;
              END IF;
         END PROCESS;
END rtl_arc;