basic_dff.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY basic_dff IS 
           PORT (d,clk  : IN  std_logic;
		 q,qb   : OUT std_logic);
END basic_dff;

ARCHITECTURE rtl_arc OF basic_dff IS
BEGIN
	 PROCESS (clk)
         BEGIN
              IF (clk'event AND clk ='1') THEN
                  q  <= d;
                  qb <= NOT d;
              END IF;
         END PROCESS;
END rtl_arc;