vector_to_int.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY vector_to_int IS
           PORT (input : IN  std_logic_vector(7 DOWNTO 0);
                 flag  : OUT  boolean;
                 q     : OUT integer);
END vector_to_int;

ARCHITECTURE behave OF vector_to_int IS
BEGIN
     PROCESS(input)
     VARIABLE  tmp : integer := 0;
     BEGIN
              flag <= false;
              FOR i IN 7 DOWNTO 0 LOOP
                  tmp := tmp * 2;
                  IF (input(i)= '1') THEN
                     tmp := tmp +1;
                  ELSIF (input(i)/= '0') THEN
                     flag <= true;
                  END IF;
              END LOOP;
              q <= tmp;
      END PROCESS;
END behave;