logic_and.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY logic_and IS
           PORT (input : IN std_logic_vector(7 DOWNTO 0);
                 q : OUT std_logic);
END logic_and;

ARCHITECTURE behave OF logic_and IS
BEGIN
     PROCESS(input)
     VARIABLE  tmp : std_logic;
     VARIABLE  i : integer;
     BEGIN
          tmp := '1';
          i := 0;
          WHILE (i<8) LOOP
                tmp := tmp AND input(i);
                i :=i+1;
          END LOOP;
          q <= tmp;
     END PROCESS;
END behave;