example.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY example IS 
END example;

ARCHITECTURE behave OF example IS
     SIGNAL  a,b  : std_logic;
BEGIN
     a <= '0';
     P1: PROCESS
     BEGIN
          WAIT UNTIL b = '1';        -- line 1
               a <= '1' AFTER 10 ns;
          WAIT UNTIL b = '0';        -- line 2
               a <= '0' AFTER 10 ns;
     END PROCESS;
     P2: PROCESS
     BEGIN
          WAIT UNTIL a = '0';        -- line 3
               b <= '0' AFTER 10 ns;
          WAIT UNTIL a = '1';        -- line 4
               b <= '1' AFTER 10 ns;
     END PROCESS;
END behave;