clk_generator.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY clk_generator IS 
           PORT (clk  : OUT std_logic);
END clk_generator;

ARCHITECTURE example OF clk_generator IS
BEGIN
     PROCESS
     BEGIN
          WAIT FOR 125 ns;
               clk <= '0';
          WAIT FOR 125 ns;
               clk <= '1';
     END PROCESS;
END example;