example.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 41 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY example IS 
END example;

ARCHITECTURE behave OF example IS
     SIGNAL  a,b  : std_logic;
BEGIN
         a <= '0';
         P1: PROCESS
         BEGIN
              WAIT UNTIL (b = '1') FOR 1 us;
                   ASSERT (b = '1')
                   REPORT "b timed out at '1'."
                   SEVERITY error;
                   a <= '1' AFTER 10 ns;
              WAIT UNTIL (b = '0') FOR 1 us;
                   ASSERT (b = '0')
                   REPORT "b timed out at '0'."
                   SEVERITY error;
                   a <= '0' AFTER 10 ns;
         END PROCESS;
         P2: PROCESS
         BEGIN
              WAIT UNTIL (a = '0') FOR 1 us;
                   ASSERT (a = '0')
                   REPORT "a timed out at '0'."
                   SEVERITY error;
                   b <= '0' AFTER 10 ns;
              WAIT UNTIL (a = '1') FOR 1 us;
                   ASSERT (a = '1')
                   REPORT "a timed out at '1'."
                   SEVERITY error;
                   b <= '1' AFTER 10 ns;
         END PROCESS;
END behave;