reset_dff2.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY reset_dff2 IS 
           PORT (clk,reset  : IN  std_logic;
                 d  : IN  std_logic;
                 q  : OUT std_logic);
END reset_dff2;

ARCHITECTURE rtl OF reset_dff2 IS
BEGIN
     PROCESS
     BEGIN
              WAIT UNTIL clk'event AND clk = '1';
              IF (reset = '1') THEN 
                  q <= '0';
              ELSE
                  q <= d;
              END IF;
     END PROCESS;
END rtl;