mux4.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY mux4 IS 
           PORT (d0  : IN  std_logic_vector(3 downto 0);
                 d1  : IN  std_logic_vector(3 DOWNTO 0);
                 d2  : IN  std_logic_vector(3 DOWNTO 0);
                 d3  : IN  std_logic_vector(3 DOWNTO 0);
	         sel : IN  std_logic_vector(1 DOWNTO 0);
		 q   : OUT std_logic_vector(3 DOWNTO 0));
END mux4;

ARCHITECTURE rtl OF mux4 IS
BEGIN
     PROCESS(d0,d1,d2,d3,sel)
     BEGIN
              CASE sel IS
                   WHEN "00" => q <= d0;
                   WHEN "01" => q <= d1;
                   WHEN "10" => q <= d2;
                   WHEN "11" => q <= d3;
                   WHEN OTHERS => q <= NULL;
              END CASE;
     END PROCESS;
END rtl;