mux4.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY mux4 IS 
           PORT (d0  : IN  std_logic_vector(3 downto 0);
                 d1  : IN  std_logic_vector(3 DOWNTO 0);
                 d2  : IN  std_logic_vector(3 DOWNTO 0);
                 d3  : IN  std_logic_vector(3 DOWNTO 0);
	         sel : IN  std_logic_vector(1 DOWNTO 0);
		 q   : OUT std_logic_vector(3 DOWNTO 0));
END mux4;

ARCHITECTURE rtl OF mux4 IS
BEGIN
     PROCESS(d0,d1,d2,d3,sel)
     BEGIN
          IF (sel = "00") THEN
              q <= d0;
          ELSIF (sel = "01") THEN
              q <= d1;
          ELSIF (sel = "10") THEN
              q <= d2;
          ELSE
              q <= d3;
          END IF;
     END PROCESS;
END rtl;