example.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY example IS 
           PORT (a1,b1 : IN  std_logic;
                 a2,b2 : IN  std_logic;
		 c1    : OUT std_logic;
		 c2    : OUT std_logic);
END example;

ARCHITECTURE behave OF example IS
         COMPONENT and_gate
            GENERIC (delay  : time);
            PORT (a  : IN  std_logic;
                  b  : IN  std_logic;
		  c  : OUT std_logic);
         END COMPONENT;
BEGIN
	 U1:and_gate GENERIC MAP (6 ns)
             PORT MAP (a1,b1,c1);
	 U2:and_gate GENERIC MAP (8 ns)
             PORT MAP (a2,b2,c2);   
END behave;