mux4.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY mux4 IS 
           PORT (d0,d1,d2,d3 : IN  std_logic;
	         sel : IN  std_logic_vector(1 DOWNTO 0);
		 q   : OUT std_logic);
END mux4;

ARCHITECTURE rtl OF mux4 IS
BEGIN
     WITH sel SELECT
          q  <= d0  WHEN   "00",
                d1  WHEN   "01",
                d2  WHEN   "10",
                d3  WHEN   "11",
                'Z' WHEN   OTHERS;
END rtl;