gate_circuits.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY gate_circuits IS 
           PORT (a,b   : IN  std_logic;
                 x,y,z : OUT std_logic);
END gate_circuits;

ARCHITECTURE behave OF gate_circuits IS
BEGIN
     P1:PROCESS(a,b)
     BEGIN
          x <= a AND b;
     END PROCESS P1;
     P2:PROCESS(a,b)
     BEGIN
          y <= a OR b;
     END PROCESS P2;
     P3:PROCESS(a,b)
     BEGIN
          z <= a XOR b;
     END PROCESS P3;
END behave;