example.vhd

数字逻辑基础与Verilog设计,针对verilog语言的特点

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY example IS 
       PORT (a : IN  std_logic;
	     b : OUT std_logic);
END example;

ARCHITECTURE behave OF example IS
BEGIN
        ASSERT false
        REPORT "This entity is a example to descript assert statement"
        SEVERITY note;
        b <= a;
END behave;