example.vhd

来自「数字逻辑基础与Verilog设计,针对verilog语言的特点」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY example IS 
           PORT (in1,in2 : IN  std_logic;
		 out1    : OUT std_logic);
END example;

ARCHITECTURE structure OF example IS
         COMPONENT and_gate
            GENERIC (delay  : time);
            PORT (a  : IN  std_logic;
                  b  : IN  std_logic;
		  c  : OUT std_logic);
         END COMPONENT;
BEGIN
	U1:and_gate GENERIC MAP (10 ns)
           PORT MAP (in1,in2,out1);
END structure;