mmm16.v

verilog编写的16qam调制程序

module mmm16(clk,reset,clr,din,clk500hz,nrst,iout,x_t);
input clk,reset,clr ,din,clk500hz,nrst;//clk为20Mhz
output  iout,x_t;
reg dout;
wire[3:0] din;  //0001
reg[3:0] rfsr;
wire[10:0] i;
reg clk1;
integer cnt1=0; //分频计计数
reg [1:0] cnt2; //4位寄存计数
reg [3:0] x_t,x_t_1;
wire[10:0] iout;
always @(posedge clk) //100分频
begin
   if(cnt1<50)
   begin
      clk1<=1'b0;
      cnt1=cnt1+1;
   end
   else if(cnt1<99)
   begin
      clk1<=1'b1;
      cnt1=cnt1+1;
   end
   else
      cnt1=0;
end
always@(posedge clk1 or posedge reset)//15位m序列（1000，1001，1010，1111）
    if(reset==1)
      rfsr<=din;
    else
      begin
      dout<=rfsr[0];
      rfsr[3]<=rfsr[0]^rfsr[1];
      rfsr[2:0]<=rfsr[3:1];
      end
always @(posedge clk1 or posedge clr) //延迟5个周期，4位寄存
   begin
   if(clr) begin
		 x_t <= 0;
		 x_t_1 <= 0;
		 cnt2 <= 0;
	end
	else begin
	   cnt2 <= cnt2 + 1;
	   x_t_1[3:0] <= {x_t_1[2:0], dout};
		if(cnt2 == 0)
		  x_t <= x_t_1;
		else 
		  x_t <= x_t;
	end
end
testboth b1(.clk(clk500hz),.nrst(nrst),.inbit(x_t),.i(i));
assign iout=i;

endmodule