first.rpt

verilog 初学者原代码

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  30     37    C     OUTPUT      t        0      0   0    1    0    0    0  ledout0
  31     35    C     OUTPUT      t        0      0   0    1    0    0    0  ledout1
  33     64    D     OUTPUT      t        0      0   0    1    0    0    0  ledout2
  34     61    D     OUTPUT      t        0      0   0    1    0    0    0  ledout3
  35     59    D     OUTPUT      t        0      0   0    1    0    0    0  ledout4
  36     57    D     OUTPUT      t        0      0   0    1    0    0    0  ledout5
  37     56    D     OUTPUT      t        0      0   0    1    0    0    0  ledout6
  39     53    D     OUTPUT      t        0      0   0    1    0    0    0  ledout7


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       c:\maxplus2\files\first.rpt
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** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

             Logic cells placed in LAB 'C'
        +--- LC37 ledout0
        | +- LC35 ledout1
        | | 
        | |   Other LABs fed by signals
        | |   that feed LAB 'C'
LC      | | | A B C D E F G H |     Logic cells that feed LAB 'C':

Pin
56   -> * - | - - * - - - - - | <-- keyin0
57   -> - * | - - * - - - - - | <-- keyin1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       c:\maxplus2\files\first.rpt
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** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                     Logic cells placed in LAB 'D'
        +----------- LC64 ledout2
        | +--------- LC61 ledout3
        | | +------- LC59 ledout4
        | | | +----- LC57 ledout5
        | | | | +--- LC56 ledout6
        | | | | | +- LC53 ledout7
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'D'
LC      | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'D':

Pin
58   -> * - - - - - | - - - * - - - - | <-- keyin2
60   -> - * - - - - | - - - * - - - - | <-- keyin3
61   -> - - * - - - | - - - * - - - - | <-- keyin4
63   -> - - - * - - | - - - * - - - - | <-- keyin5
64   -> - - - - * - | - - - * - - - - | <-- keyin6
65   -> - - - - - * | - - - * - - - - | <-- keyin7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       c:\maxplus2\files\first.rpt
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** EQUATIONS **

keyin0   : INPUT;
keyin1   : INPUT;
keyin2   : INPUT;
keyin3   : INPUT;
keyin4   : INPUT;
keyin5   : INPUT;
keyin6   : INPUT;
keyin7   : INPUT;

-- Node name is 'ledout0' 
-- Equation name is 'ledout0', location is LC037, type is output.
 ledout0 = LCELL( keyin0 $  GND);

-- Node name is 'ledout1' 
-- Equation name is 'ledout1', location is LC035, type is output.
 ledout1 = LCELL( keyin1 $  GND);

-- Node name is 'ledout2' 
-- Equation name is 'ledout2', location is LC064, type is output.
 ledout2 = LCELL( keyin2 $  GND);

-- Node name is 'ledout3' 
-- Equation name is 'ledout3', location is LC061, type is output.
 ledout3 = LCELL( keyin3 $  GND);

-- Node name is 'ledout4' 
-- Equation name is 'ledout4', location is LC059, type is output.
 ledout4 = LCELL( keyin4 $  GND);

-- Node name is 'ledout5' 
-- Equation name is 'ledout5', location is LC057, type is output.
 ledout5 = LCELL( keyin5 $  GND);

-- Node name is 'ledout6' 
-- Equation name is 'ledout6', location is LC056, type is output.
 ledout6 = LCELL( keyin6 $  GND);

-- Node name is 'ledout7' 
-- Equation name is 'ledout7', location is LC053, type is output.
 ledout7 = LCELL( keyin7 $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                c:\maxplus2\files\first.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = on
   Rules                                  = EPLD Rules


Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:04
   Design Doctor                          00:00:00
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,782K